1. Field
Embodiments of the invention relate to the field of computing systems architecture. More specifically, embodiments of the invention relate to the field of serial device attachment, such as, for example serial advanced technology attachment (SATA).
2. Background Information
FIG. 1 is a block diagram showing a prior art computer system architecture 100. The computer system architecture includes a host device 105, a serial advanced technology attachment (SATA) host bus adapter (HBA) 110, and a plurality of serially attached devices 192, 195, 198. The plurality of serially attached devices include a first device 192, a second device 195, and an Nth Device 198.
The SATA HBA is coupled with, or otherwise in communication with, the host device, which may representatively be a computer system. The SATA HBA includes a plurality of SATA ports 190, 193, 196. The plurality of SATA ports include a first SATA port 190, a second SATA port 193, and an Nth SATA port 196. A different port is used to attach each device.
The plurality of serially attached devices are each coupled with, or otherwise in communication with, the SATA HBA through a corresponding serial interface (SI) 191, 194, 197, such as, for example, a differential signal pair. In particular, a first serial interface 191 is coupled with the first SATA port and allows the first device to communicate with the SATA HBA, a second serial interface 194 is coupled with the second SATA port and allows the second device to communicate with the SATA HBA, and an Nth serial interface 197 is coupled with the Nth SATA port and allows the Nth device to communicate with the SATA HBA.
The host device and each of the plurality of serially attached devices may exchange data through the SATA HBA. By way of example, the attached devices may include storage devices, and the host device may exchange input and/or output data (I/O) with the storage devices. The SATA HBA typically converts the I/O data into frames and FISes (frame information structures), which may be exchanged with the attached devices over the serial interfaces.
Various SATA HBAs are known in the art. FIG. 2 is a block diagram showing pertinent components of a prior art SATA HBA 210. The SATA HBA includes a host device interface 212, a direct memory access (DMA) engine 214, a plurality of separate SATA protocol engines 216, 218, 220, and a corresponding plurality of SATA ports 290, 293, 296.
The plurality of separate SATA protocol engines includes a first SATA protocol engine 216, a second SATA protocol engine 218, and an Nth SATA protocol engine 220. The plurality of SATA ports include a first SATA port 290, a second SATA port 293, and an Nth SATA port 296. Notice that each SATA port that is supported by the SATA HBA has a corresponding SATA protocol engine. Typically, N may be sixteen.
Each of the SATA protocol engines includes a set of serial digital transport layer control logic, serial digital link layer control logic, and a serial physical interface plant. In particular, the first SATA protocol engine includes a first set of such logic 222, 228, the second protocol engine includes a second set of such logic 224, 230, and the Nth protocol engine, such as, for example, the sixteenth SATA protocol engine, includes an Nth set of such logic 226, 232.
Representative operations that may be performed by each of the serial digital transport layer control logics may include communicating with the DMA engine to exchange data with the host device, performing transport layer protocol processing, generating frames and FISes, parsing frames and FISes, and performing flow control. Additionally, the serial digital transport layer control logics are often implemented by firmware, may tend to interrupt the processor and increase latency, such as, for example, by interrupting the processor to read a tag, look up context information, etc. Still further, each of the transport layer logics may include transmit and receive buffers to store data, headers, control parameters, and the like.
Accordingly, there tends to be a substantial amount of replication of serial digital transport layer control logic across different SATA protocol engines. Such replication of logic may tend to increase the physical size and/or the cost of the SATA HBA. Additionally, in such an HBA, the DMA engine may include logic to multiplex data among the different SATA ports, and may have relatively large buffers, which may both tend to increase the complexity of the DMA engine.